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PCA9538 8-bit I2C and SMBus low power I/O port with interrupt and reset
Product data sheet Supersedes data of 2004 Sep 30 2004 Oct 05
Philips Semiconductors
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
DESCRIPTION
The PCA9538 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. I/O expanders provides a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. The PCA9538 consists of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active HIGH or Active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the input port register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and different address range. The PCA9538 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without depowering the device. Two hardware pins (A0 and A1) vary the fixed I2C address and allow up to four devices to share the same I2C/SMBus.
FEATURES
* 8-bit I2C GPIO with interrupt and reset * Operating power supply voltage range of 2.3 V to 5.5 V * 5 V tolerant I/Os * Polarity inversion register * Active LOW interrupt output * Active LOW reset input * Low stand-by current * Noise filter on SCL/SDA inputs * No glitch on power-up * Internal power-on reset * 8 I/O pins which default to 8 inputs * 0 kHz to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Offered in three different packages: SO16, TSSOP16, and
HVQFN16 exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO (wide) 16-Pin Plastic TSSOP 16-Pin Plastic HVQFN TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C ORDER CODE PCA9538D PCA9538PW PCA9538BS TOPSIDE MARK PCA9538D PCA9538 9538 DRAWING NUMBER SOT162-1 SOT403-1 SOT629-1
Standard packing quantities and other packing data are available at www.standardproducts.philips.com/packaging. I2C-bus is a trademark of Philips Semiconductors Corporation. SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
PIN CONFIGURATION -- SO, TSSOP
A0 1 A1 2 16 VDD 15 SDA 14 SCL 13 INT 12 I/O7
PIN CONFIGURATION -- HVQFN
A1 16 A0 15 VDD 14 SDA 13 12 SCL 11 INT 10 I/O7 9 5 6 7 8 I/O6 I/O5
RESET 3 I/O0 4 I/O1 5 I/O2 6 I/O3 7 VSS 8
RESET I/O0 I/O1
1 2 3 4
11 I/O6 10 I/O5 9 I/O4 I/O2
SW02172
I/O3
VSS I/O4
Figure 1. Pin configuration -- SO, TSSOP
TOP VIEW
SW02173
Figure 2. Pin Configuration -- HVQFN
PIN DESCRIPTION
SO, TSSOP PIN NUMBER 1 2 3 4-7 8 9-12 13 14 15 16 HVQFN PIN NUMBER 15 16 1 2-5 6 7-10 11 12 13 14 SYMBOL A0 A1 RESET I/O0-3 VSS I/O4-7 INT SCL SDA VDD Address input 0 Address input 1 Active LOW reset input I/O0 to I/O3 Supply ground I/O4 to I/O7 Interrupt output (open drain) Serial clock line Serial data line Supply voltage FUNCTION
BLOCK DIAGRAM
PCA9538
A0 A1 I/O0 I/O1 SCL SDA I/O2 INPUT FILTER I2C/SMBUS CONTROL 8-BIT INPUT/ OUTPUT PORTS I/O3 I/O4 I/O5 I/O6 I/O7 VDD RESET VSS LP FILTER NOTE: ALL I/Os ARE SET TO INPUTS AT RESET POWER-ON RESET INT VCC
WRITE pulse READ pulse
SW02174
Figure 3. Block diagram
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
REGISTERS Command Byte
Command 0 1 2 3 Protocol Read byte Read/write byte Read/write byte Read/write byte Function Input port register Output port register Polarity inversion register Configuration register
Power-on Reset
When power is applied to VDD, an internal power-on reset holds the PCA9538 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage.
RESET Input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tW. The PCA9538 registers and SMBus/I2C state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used.
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
Register 0 - Input Port Register
bit
default
I7 X
I6 X
I5 X
I4 X
I3 X
I2 X
I1 X
I0 X
Interrupt Output
The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the input port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value `X' is determined by the externally applied logic level.
Register 1 - Output Port Register
bit
default
O7 1
O6 1
O5 1
O4 1
O3 1
O2 1
O1 1
O0 1
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, NOT the actual pin value.
Register 2 - Polarity Inversion Register
bit
default
N7 0
N6 0
N5 0
N4 0
N3 0
N2 0
N1 0
N0 0
This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with `1'), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a `0'), the Input Port data polarity is retained.
Register 3 - Configuration Register
bit
default
C7 1
C6 1
C5 1
C4 1
C3 1
C2 1
C1 1
C0 1
This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
SIMPLIFIED SCHEMATIC OF I/O0 TO I/O7
DATA FROM SHIFT REGISTER CONFIGURATION REGISTER DATA FROM SHIFT REGISTER D FF WRITE CONFIGURATION PULSE WRITE PULSE CK Q D FF CK Q Q2 I/O0 TO I/O7 Q Q Q1 ESD PROTECTION DIODE OUTPUT PORT REGISTER DATA VDD
OUTPUT PORT REGISTER INPUT PORT REGISTER D FF READ PULSE CK Q Q
ESD PROTECTION DIODE
VSS
INPUT PORT REGISTER DATA
TO INT
DATA FROM SHIFT REGISTER WRITE POLARITY PULSE
D FF CK
Q
POLARITY REGISTER DATA
Q
POLARITY INVERSION REGISTER
SU01784
NOTE: At Power-on Reset, all registers return to default values. Figure 4. Simplified schematic of I/O0 to I/O7
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low impedance paths that exist between the pin and either VDD or VSS.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
Device address
SLAVE ADDRESS
1
1
1
0
0
A1
A0 R/W
FIXED
HARDWARE SELECTABLE
SW02175
Figure 5. PCA9538 address
Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figures 6 and 7. Data is read from the PCA9538 registers using the read mode as shown in Figures 8 and 9. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.
SCL
1
2
3
4
5
6
7
8
9 command byte
slave address
data to port
SDA
S
1
1
1
0
0
A1
A0
0 R/W
A
0
0
0
0
0
0
0
1
A acknowledge from slave
DATA 1
A
P
start condition
acknowledge from slave
acknowledge from slave
WRITE TO PORT
DATA OUT FROM PORT tpv
DATA 1 VALID
SW02176
Figure 6. WRITE to output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
command byte
data to register
SDA
S
1
1
1
0
0
A1
A0
0 R/W
A
0
0
0
0
0
0
1
1/0
A acknowledge from slave
DATA
A
P
start condition
acknowledge from slave
acknowledge from slave
DATA TO REGISTER
SW02177
Figure 7. WRITE to configuration or polarity inversion registers
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
slave address
acknowledge from slave
acknowledge from slave
slave address
acknowledge from slave
data from register
acknowledge from master
S
1
1
1
0
0
A1 A0
0 R/W
A
COMMAND BYTE
A
S
1
1
1
0
0
A1 A0
1 R/W
A
DATA first byte
A
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter data from register no acknowledge from master
DATA last byte
NA
P
SW02178
Figure 8. READ from register
SCL
1
2
3
4
5
6
7
8
9 data from port data from port
slave address
SDA
S
1
1
1
0
0
A1
A0
1 R/W
A acknowledge from slave
DATA 1
A acknowledge from master
DATA 4
NA
P stop condition
start condition
no acknowledge from master
READ FROM PORT
DATA INTO PORT tph
DATA 2
DATA 3 tps
DATA 4
INT
tiv
tir
SW02179
NOTES: 1. This figure assumes the command byte has previously been programmed with 00h. 2. Transfer of data can be stopped at any moment by a stop condition. Figure 9. READ input port register
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
TYPICAL APPLICATION
VDD (5 V) VDD SCL SDA MASTER CONTROLLER INT IRESET GND I/O3 I/O4 SUBSYSTEM 2 (e.g. counter) 10 k 10 k 10 k 10 k VDD SCL SDA I/O1 INT IRESET I/O2 RESET INT I/O0 SUBSYSTEM 1 (e.g. temp sensor) 100 k (x3)
2 k
PCA9538
I/O5 A Controlled Switch (e.g. CBT device) ENABLE I/O7 A0 B
I/O6 A1
VSS
ALARM SUBSYSTEM 3 (e.g. alarm system)
NOTE: Device address configured as 1110000 for this example I/O0, I/O2, I/O3, configured as outputs I/O1, I/O4, I/O5, configured as inputs I/O06, I/O7, are not used and need 100 k pull-up resistors to protect them from floating.
VDD
SW02180
Figure 10. Typical application
Minimizing IDD when the I/O is used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 10. Since the LED acts as a diode, when the LED is off the I/O VIN is about 1.2 V less than VDD. The supply current , IDD, increases as VIN becomes lower than VDD and is specified as IDD in the DC characteristics table. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 11 shows a high value resistor in parallel with the LED. Figure 12 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VIN at or above VDD and prevents additional supply current consumption when the LED is off.
VDD
3.3 V
5V
LED VDD
100 k VDD LED
LEDx
LEDx
SW02086
SW02087
Figure 11. High value resistor in parallel with the LED
Figure 12. Device supplied by a lower voltage
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDD II VI/O II/O IDD ISS Ptot Tstg Tamb TJ(MAX) Supply voltage DC input current DC voltage on an I/O DC output current on an I/O Supply current Supply current Total power dissipation Storage temperature range Operating ambient temperature Maximum junction temperature PARAMETER CONDITIONS MIN -0.5 -- VSS - 0.5 -- -- -- -- -65 -40 -- MAX 6.0 20 5.5 50 85 100 200 +150 +85 +125 UNIT V mA V mA mA mA mW C C C
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under "Handling MOS devices".
DC CHARACTERISTICS
SYMBOL Supplies VDD IDD Istbl Istbh VPOR VIL VIH IOL IL CI I/Os VIL VIH Supply voltage Supply current Standby current Standby current
VDD = 2.3 to 5.5 V; VSS = 0 V; Tamb = -40 to +85 C; unless otherwise specified. PARAMETER CONDITIONS MIN 2.3 Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs No load; VI = VDD or VSS -- -- -- -- -0.5 0.7 VDD VOL = 0.4V VI = VDD = VSS VI = VSS 3 -1 -- -0.5 2.0 VOL = 0.5 V; VDD = 2.3 V; Note 2 VOL = 0.7 V; VDD = 2.3 V; Note 2 IO OL LOW-level LOW level output current VOL = 0.5 V; VDD = 4.5 V; Note 2 VOL = 0.7 V; VDD = 4.5 V; Note 2 VOL = 0.5 V; VDD = 3.0 V; Note 2 VOL = 0.7 V; VDD = 3.0 V; Note 2 IOH = -8 mA; VDD = 2.3 V; Note 3 IOH = -10 mA; VDD = 2.3 V; Note 3 VO OH HIGH level output voltage HIGH-level IOH = -8 mA; VDD = 3.0 V; Note 3 IOH = -10 mA; VDD = 3.0 V; Note 3 IOH = -8 mA; VDD = 4.5 V; Note 3 IOH = -10 mA; VDD = 4.5 V; Note 3 IIL CI IOL VIL VIH ILI Input leakage current Input capacitance LOW-level output current LOW-level input voltage HIGH-level input voltage Input leakage current VOL = 0.4 V VI = VDD = VSS 8 10 8 10 8 10 1.8 1.7 2.6 2.5 4.1 4.0 -1 -- 3 -0.5 2.0 -1 TYP -- 104 0.25 0.25 1.5 -- -- tbd -- 5 -- -- 10 13 17 24 14 19 -- -- -- -- -- -- -- 5 tbd -- -- -- MAX 5.5 175 1 1 1.65 0.3 VDD 5.5 -- +1 10 0.8 5.5 -- -- -- -- -- -- -- -- -- -- -- -- 1 10 -- 0.8 5.5 1 UNIT V A A A V V V mA A pF V V mA mA mA mA mA mA V V V V V V A pF mA V V A
Power-on reset voltage (Note 1) LOW-level input voltage HIGH-level input voltage LOW-level output current Leakage current Input capacitance LOW-level input voltage HIGH-level input voltage
Input SCL; input/output SDA
Interrupt INT Select Inputs A0, A1, and RESET
NOTES: 1. VDD must be lowered to 0.2 V in order to reset part. 2. Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 3. The total current sourced by all I/Os must be limited to 85 mA.
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
AC SPECIFICATIONS
SYMBOL fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tF tR tSP Port Timing tPV tPS tPH tIV tIR RESET tW tREC tRESET Reset pulse width Reset recovery time Time to reset 4 0 400 -- -- -- 4 0 400 -- -- -- ns ns ns Output data valid Input data setup time Input data hold time Interrupt valid Interrupt reset -- 100 1 -- -- 200 -- -- 4 4 -- 100 1 -- -- 200 -- -- 4 4 ns ns s s s Operating frequency Bus free time between STOP and START conditions Hold time after (repeated) START condition Repeated START condition setup time Setup time for STOP condition Data in hold time Valid time for ACK Data setup time Clock LOW period Clock HIGH period Clock/Data fall time Clock/Data rise time Pulse width of spikes that must be suppressed by the input filters condition2 Data out valid time3 PARAMETER STANDARD MODE I2C-bus MIN 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 -- -- -- MAX 100 -- -- -- -- -- 3.45 -- -- -- -- 300 1000 50 FAST MODE I2C-bus MIN 0 1.3 0.6 0.6 0.6 0 0.1 50 100 1.3 0.6 20 + 0.1 Cb1 20 + 0.1 Cb --
1
UNITS 400 -- -- -- -- -- 0.9 -- -- -- -- 300 300 50 kHz s s s s ns s ns ns s s ns ns ns
MAX
Interrupt Timing
NOTES: 1. Cb = total capacitance of one bus line in pF. 2. tVD;ACK = time for Acknowledgement signal from SCL low to SDA (out) low. 3. tVD;DAT = minimum time for SDA data out to be valid following SCL low.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
SU00645
Figure 13. Definition of timing
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
START SCL
ACK OR READ CYCLE
SDA
30% tRESET RESET 50% tREC tW tRESET I/Ox 50% 50% 50%
I/O configured as inputs
SW02340
Figure 14. Definition of RESET timing
70 % SCL 2 1 0 A P 30 %
SDA tPS tPH
INPUT tIV tIR
50 %
INT
SW02329
Figure 15. Expanded view of Read input port register
70 % SCL 2 1 0 A P 30 %
SDA tPV
OUTPUT
50 %
SW02330
Figure 16. Expanded view of Write to output port register
2004 Oct 05
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (S)
t
SU;STA
t
LOW
t HIGH
1 / f SCL
SCL
t
BUF
tr
t f
SDA
t HD;STA
t
SU;DAT
t
HD;DAT
t
tSU;STO VD;DAT t VD;ACK
SW02210
Figure 17. I2C-bus timing diagram; rise and fall times refer to VIL and VIH
TEST CIRCUITS
VDD RL = 500 VI PULSE GENERATOR RT D.U.T. CL 50 pF VO VDD Open
DEFINITIONS
RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators.
SW02181
Figure 18. Test circuitry for switching times
From Output Under Test CL = 50 pF
500
2VDD S1 Open GND
500
Load Circuit
TEST tpv
S1 2 VDD
SA00652
Figure 19. Test circuit
2004 Oct 05
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
2004 Oct 05
14
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
2004 Oct 05
15
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
2004 Oct 05
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Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
REVISION HISTORY
Rev _3 Date 20041005 Description Product data sheet (9397 750 14176). Supersedes data of 2004 Sep 30 (9397 750 14049).
* Upgrade status to "Product data sheet"
_2 _1 20040930 20040820 Objective data sheet (9397 750 14049). Supersedes data of 2004 Aug 20 (9397 750 12881). Objective data sheet (9397 750 12881).
Modifications:
2004 Oct 05
17
Philips Semiconductors
Product data sheet
8-bit I2C and SMBus low power I/O port with interrupt and reset
PCA9538
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 10-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 14176
Philips Semiconductors
2004 Oct 05 18

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